This invention relates to transient data recording, and more particularly, to a storage device for temporarily storing high speed samples of an analog input signal.
The development of the silicon planar process has produced a virtual revolution of performance and cost in the field of digital and analog signal processing. One important step of this advance was the development of charge-transfer structures providing storage for a large number of samples of an input signal. In addition to storage, charge-transfer devices provide another advantage in signal processing systems because they need not operate in real time, i.e., increments of phase are determined by an externally applied train of clock signals rather than by a physical phenomenon associated with the device. Therefore, it is possible to perform signal processing with these devices using a task-shared computer. Serial charge-transfer structures are limited in length by imperfect charge-transfer efficiency which causes a cumulative misplacement of the charges representing the input signal. Furthermore, transfer-gate capacitance increases in long serial registers operated at high frequencies. These problems have been alleviated by using a serial-parallel-serial (SPS) organization, and by multiplexing charge-transfer arrays; however, peripheral circuitry such as input circuits, output amplifiers, and particularly circuits for the generation and distribution of clock signals, limit the maximum clock frequency of the device.
Accordingly it is an object of the present invention to provide an improved signal acquisition circuit.
It is another object of the present invention to provide an improved signal acquisition circuit utilizing multiplexed data storage for increasing the rate at which an analog input signal is sampled.
Another object of the instant invention is to provide an improved multiplexed analog delay line storage element in a signal acquisition circuit utilizing a common clock signal for signal propagation in multiplexed delay lines.
Another object of the present invention is to provide an improved analog signal acquisition system utilizing multiplexed charge-coupled device delay lines having common clock drivers.
The present invention, in accordance with one aspect thereof, provides two charge transfer delay line devices on a common substrate having common clock signal drive lines, and each receiving a common analog input signal. One of the devices is provided with an additional set of transfer electrodes at the input circuit which facilitates multiplexed sampling of the input signal using a single driver circuit with output signals operating at one-half the multiplexed sample rate. Subsequent to input sampling, all transfers of the input signal within the two delay line elements are simultaneous, a single set of drive circuits performing charge transfer, output resetting and output sampling.